← ClaudeAtlas

assembly-toolchain-performance-and-simdlisted

Use when wiring assembly to C (calling conventions and ABIs: System V, Windows x64, AAPCS64, RISC-V), choosing or fighting an assembler (GAS vs NASM, AT&T vs Intel syntax, linkers, objdump), reading disassembly and recognizing compiler patterns, or optimizing at the instruction level. Covers the out-of-order/superscalar mental model, latency vs throughput, caches and memory, branch prediction, alignment, and SIMD/vector programming — SSE/AVX/AVX-512/AVX10, NEON/SVE2/SME, RISC-V RVV — and how to write SIMD well.
adammatthewsteinberger/vibey-skills · ★ 1 · AI & Automation · score 72
Install: claude install-skill adammatthewsteinberger/vibey-skills
# Assembly Programming: ABIs, Toolchain, Disassembly, Performance, and SIMD > **Part 2 of 4** of the *Assembly Programming* reference (plugin `assembly-programming`), covering §6–§10. Sibling skills: `assembly-fundamentals-and-isas` (§0–§5), `assembly-systems-crypto-and-inline` (§11–§14), `assembly-reference` (§15–§20). Section numbers are shared across the set; a reference written as §N → `skill` points into that sibling skill. > > **Currency:** Verified August 2026. See §17 → `assembly-reference` for the currency snapshot and what goes stale first. > **How to read this.** Reference, not tutorial. Sections are independent. Three markers: > - **[DURABLE]** — machine organization, algorithms, or a lesson that has held since the > 1970s. Does not expire. > - **[ISA]** — specific to x86-64, AArch64, RISC-V, or a particular microarchitecture. > Verify against the vendor's current manual. > - **[CONTESTED]** — practitioners genuinely disagree, usually about how much hand-written > assembly is justified. > > **⚠️ GOTCHA** boxes mark the mistakes that produce silent corruption, ABI violations, > or code that is slower than the C you replaced. > > **The three framings that organize everything below:** > 1. **The instruction set is an interface, not the machine.** The CPU you're actually > programming is out-of-order, superscalar, speculative, and cached. Your instructions > are decoded into µops, reordered, and executed in parallel. Reasoning about assembly > as "the