verification-methodologylisted

Use when designing verification environments, planning coverage-driven closure, or architecting UVM testbenches. Covers constrained-random stimulus, functional coverage models, assertion-based verification, formal property checking, and coverage closure planning. Do not use for RTL design flow (use chip-design-flow) or SoC integration (use soc-integration).
dtsong/my-claude-setup · ★ 5 · AI & Automation · score 76

Install: claude install-skill dtsong/my-claude-setup

# Verification Methodology ## Purpose Design verification environments and coverage-driven closure plans that prove functional correctness of RTL designs through structured stimulus generation, coverage modeling, and assertion-based checking. ## Scope Constraints Reviews RTL specifications and existing verification infrastructure. Does not execute simulations or formal tools. Does not modify RTL or testbench code. ## Inputs - RTL design specification or block description - Verification requirements (features to verify, corner cases) - Target coverage metrics (functional, code, assertion) - Existing testbench infrastructure, if any - Formal verification scope, if applicable ## Input Sanitization No user-provided values are used in commands or file paths. All inputs are treated as read-only analysis targets. ## Procedure ### Progress Checklist - [ ] Step 1: Define verification plan - [ ] Step 2: Architect UVM testbench - [ ] Step 3: Design coverage model - [ ] Step 4: Plan constrained-random stimulus - [ ] Step 5: Define assertion strategy - [ ] Step 6: Plan coverage closure ### Step 1: Define Verification Plan - Extract features from specification and enumerate verification items. - Classify each item by complexity and risk (high/medium/low). - Map features to verification methods: directed test, constrained-random, formal. - Define pass/fail criteria for each verification item. - Set coverage targets per feature group. ### Step 2: Architect UVM Testbench - Defin