verilator-simulationlisted

Use when planning or reviewing Verilator-based simulation workflows for SystemVerilog designs. Covers lint analysis, simulation setup, trace/waveform debugging, coverage-driven verification, and C++ co-simulation. Do not use for commercial EDA tools (use verification-methodology) or RTL design flow (use chip-design-flow).
dtsong/my-claude-setup · ★ 5 · AI & Automation · score 76

Install: claude install-skill dtsong/my-claude-setup

# Verilator Simulation ## Purpose Guide Verilator-specific simulation workflows for SystemVerilog designs, from static lint analysis through simulation execution, waveform debugging, coverage closure, and C++ co-simulation integration. ## Scope Constraints Reviews RTL source, testbenches, and Makefile/build infrastructure. Does not execute Verilator or modify design files. Does not cover commercial simulators (VCS, Questa) or UVM testbench architecture — hand off to verification-methodology for those. ## Inputs - RTL design files (SystemVerilog) - Testbench files (directed or constrained-random) - Build infrastructure (Makefile, scripts) - Existing Verilator warnings or simulation logs, if any - Coverage targets or gaps to investigate ## Input Sanitization No user-provided values are used in commands or file paths. All inputs are treated as read-only analysis targets. ## Procedure ### Progress Checklist - [ ] Step 1: Lint analysis - [ ] Step 2: Simulation setup - [ ] Step 3: Trace and waveform debugging - [ ] Step 4: Coverage-driven verification - [ ] Step 5: C++ co-simulation - [ ] Step 6: Limitations and workarounds ### Step 1: Lint Analysis - Review design files with `--lint-only -Wall --timing -sv` flags. - Prioritize warnings by security impact: WIDTHTRUNC/WIDTHEXPAND (data corruption), CASEINCOMPLETE (FSM holes), UNOPTFLAT (combinational loops). - Identify justified suppressions using `/* verilator lint_off WARNING */` pragmas. - Separate design lint (strict