esp32-s3listed

# ESP32-S3 chip capabilities This skill is the **chip layer**, not a board layer. A board skill (e.g. `m5stack-cardputer-adv`) tells you what's wired to what on one specific product; this skill tells you what the ESP32-S3 silicon itself can do — the peripherals, low-power modes, memory options, and concurrency model that are the same on every ESP32-S3 board regardless of vendor. Read a board's own skill first for pin numbers and I2C addresses, then come here when the user wants to go deeper on a capability than "call the vendor's high-level library and move on" — e.g. writing a custom RMT-based protocol, tuning deep-sleep wake behavior, pinning tasks to cores, or getting real throughput out of I2S/USB. ## Not classic ESP32, not S2, not C3/C6/C5, not H2, not P4 M5Stack (and the ESP32 family generally) spans several very different chips that are easy to conflate. Get this wrong and code silently targets the wrong architecture or assumes a peripheral that doesn't exist. | Chip | Cores / arch | Wireless | Native USB | Notable extras | Not on this chip | |---|---|---|---|---|---| | **ESP32-S3** (this skill) | 2× Xtensa LX7 @ up to 240MHz + 1 low-power coprocessor core | WiFi 4 (2.4GHz only) + BLE 5 | Yes — OTG + separate USB-Serial-JTAG | SIMD/vector instructions for AI (esp-dsp/ESP-DL/TFLite Micro), ULP-RISC-V *and* ULP-FSM | Thread/Zigbee/802.15.4, WiFi 6, MIPI-DSI/CSI | | ESP32 (classic) | 2× Xtensa LX6 @ 240MHz | WiFi 4 + Bluetooth Classic + BLE 4.2 | No | Widest library/e