m5stack-core2listed

# M5Stack Core2 family development Core2 is M5Stack's 2.0" touchscreen ESP32 (classic) Controller family. Every member shares the same core: ESP32-D0WDQ6-V3 (dual-core Xtensa LX6 @ 240MHz), 16MB flash, 8MB PSRAM, an AXP192 power management IC, a 2.0" 320x240 ILI9342C IPS display with FT6336U capacitive touch, a BM8563 RTC, an NS4168 I2S amp + SPM1423 PDM mic, and a 500mAh 3.7V battery charged over a magnetic pogo-pin base. Official docs index: https://docs.m5stack.com/en/core/core2 This skill folds M5Stack's several Core2 hardware revisions into one skill rather than near-duplicate skills per revision — read "Hardware revisions" below before writing code, since the differences (which IMU chip, whether an ATECC608 crypto chip and RGB LED ring are present, physical dimensions) matter for correctness. ## Important: this is classic ESP32, not S3/P4 Unlike the other M5Stack Controller skills in this marketplace (Cardputer Adv, Tab5), Core2 runs on a **classic ESP32** (`ESP32-D0WDQ6-V3`) — Xtensa LX6, not LX7, **no native USB** (programming/serial goes through an onboard USB-UART bridge chip, not a USB-CDC peripheral on the SoC itself), no ULP-RISC-V coprocessor, and Bluetooth Classic + BLE 4.2 rather than BLE 5. For chip-level capability questions that aren't about this board's specific wiring — RMT, LEDC, I2S, ADC/touch, deep sleep and wake sources, the ULP-FSM coprocessor, PSRAM/flash config, WiFi/BT coexistence — see the **`esp32` skill** (classic ESP32), shipped in the `e