eelisted

## Core Circuit Laws ### DC Analysis ``` V = IR Ohm's Law P = VI = I²R = V²/R Power KVL: ΣV around loop = 0 Kirchhoff's Voltage Law KCL: ΣI into node = 0 Kirchhoff's Current Law ``` ### Voltage Divider ``` Vout = Vin × R2 / (R1 + R2) Rload effect: Vout_actual = Vin × (R2||Rload) / (R1 + R2||Rload) For < 1% load error: Rload > 100 × R2 ``` ### Thevenin / Norton ``` Vth = open-circuit voltage at terminals Rth = resistance seen from terminals with all sources zeroed (V→short, I→open) In = Vth / Rth ``` ### Superposition For linear circuits: activate one source at a time, zero others, sum results. --- ## Passive Components ### Resistors | Parameter | Calculation | Notes | |-|-|-| | Power derate | P_rated × 0.5 at 70°C | Derate linearly to 0 at T_max | | Noise (Johnson) | Vn = √(4kTRB) | k=1.38e-23, B=bandwidth | | Tolerance effect | ΔVout/Vout = √(ΔR1²+ΔR2²) / (R1+R2) | Worst-case RSS | **Standard E-series values:** E12 (10% tol), E24 (5%), E48 (2%), E96 (1%), E192 (0.5%) **SMD sizes:** 0201, 0402 (¼W), 0603 (⅒W), 0805 (⅛W), 1206 (¼W), 2512 (1W) ### Capacitors | Type | Voltage coeff | Temp coeff | Use case | |-|-|-|-| | C0G/NP0 | None | ±30 ppm/°C | Timing, RF, precision | | X7R | Moderate (−80% at rated V) | ±15% (-55→125°C) | Decoupling | | X5R | Higher | ±15% (-55→85°C) | Bulk, lower-cost decoupling | | Y5V | Severe (−82% at rated V) | +22/−82% | Avoid for power | | Electrolytic | Low | Varies | Bulk, low-freq