vivado-fpgalisted

## Environment Setup | Item | Notes | |-|-| | Vivado | AMD Vivado 2024.x or 2025.x — batch mode preferred for CI | | ADI HDL | Clone from `https://github.com/analogdevicesinc/hdl` | | Version mismatch | Set `ADI_IGNORE_VERSION_CHECK=1` for minor version mismatches | | Windows paths | Use forward slashes in TCL; backslashes cause parser errors | | Linux | Preferred for CI builds; AMD tools are more stable on Linux | ```bash # Vivado batch mode (Linux) vivado -mode batch -source scripts/system_project.tcl 2>&1 | tee build.log # Vivado batch mode (Windows) "C:/AMD/Vivado/2025.1/bin/vivado.bat" -mode batch -source scripts/system_project.tcl # Always run from build/ directory (ADI infra assumes this) cd fpga/build/ export ADI_IGNORE_VERSION_CHECK=1 vivado -mode batch -source ../scripts/system_project.tcl ``` ## ADI HDL Reference Design Pattern ADI's open-source HDL repo provides reference designs and reusable IP for AD9361, ADRV9002, ADRV9006, AD9371, AD9375, AD9364, ADAS1000, and many others. The infrastructure (TCL procs, AXI IP cores, DMA, CDC utilities) is the same across all parts. ### Repository Layout (ADI HDL) ``` hdl/ library/ -- Reusable IP cores (axi_ad9361, axi_adrv9001, axi_dmac, etc.) projects/ -- Reference designs (one per eval board) scripts/ -- adi_board.tcl, adi_project.tcl (key infrastructure) ``` ### Key TCL Procedures ```tcl # In adi_board.tcl / adi_project.tcl: adi_project_create <name> 0 {} {<device_part>} # Crea