build-sequential-circuitlisted

# Build Sequential Circuit Design a sequential logic circuit by identifying the required memory and state type, constructing a state diagram and transition table, deriving excitation equations for the chosen flip-flop type, implementing the circuit at the gate level using flip-flops and combinational logic, and verifying correctness through timing diagram analysis and state sequence simulation. ## When to Use - A circuit must remember past inputs or maintain internal state across clock cycles - Designing counters (binary, BCD, ring, Johnson), shift registers, or sequence detectors - Implementing a finite state machine (Mealy or Moore) from a state diagram or regular expression - Adding clocked storage elements to a combinational datapath (registers, pipeline stages) - Preparing stateful components for the simulate-cpu-architecture skill (register file, program counter, control FSM) ## Inputs - **Required**: Behavioral specification -- one of: state diagram, state table, timing diagram, regular expression to detect, or verbal description of the desired sequential behavior - **Required**: Clock characteristics -- edge-triggered (rising/falling) or level-sensitive; single clock or multi-phase - **Optional**: Flip-flop type preference (D, JK, T, or SR) - **Optional**: Reset type -- synchronous, asynchronous, or none - **Optional**: Maximum state count or bit width constraint - **Optional**: Timing constraints (setup time, hold time, maximum clock frequency) ## Procedure ##