plc-code-analysislisted

Standalone skill for multi-perspective PLC code security and quality analysis. Triggers on: "review", "audit", "analyze", "security check", "vulnerability scan", "code review", "check this code", "is this safe", "find issues" when combined with PLC, SCL, ST, LAD, FBD, Structured Text, or block context. Also triggers when the user pastes PLC code and asks for feedback, or uploads exported SimaticML XML files. This skill is independent of tia-openness-roadmap — it does not perform engineering automation. It analyzes code that has already been exported, pasted, or is accessible via the TIA Portal MCP server.
Czarnak/totally-integrated-claude · ★ 15 · AI & Automation · score 83

Install: claude install-skill Czarnak/totally-integrated-claude

# plc-code-analysis ## Goal Perform structured, multi-perspective security and quality analysis of PLC code, producing a severity-ranked findings report. Acts as an automated "second pair of eyes" for automation engineers. ## Independence from tia-openness-roadmap This skill is NOT routed by `tia-openness-roadmap`. It has its own trigger patterns and operates independently. The Openness roadmap handles engineering automation (create, modify, import/export via API). This skill handles analysis and review of existing code. The skill CAN consume code retrieved via MCP tools or Python/C# Openness exports, but it does not depend on them. ## Input recognition Claude receives PLC code in one of three ways. Identify which applies before starting analysis. ### Format 1 — Raw SCL / Structured Text The user pastes or uploads `.scl`, `.st`, or plain-text PLC code. This is the simplest case. Parse directly as text. Look for FUNCTION_BLOCK, FUNCTION, ORGANIZATION_BLOCK, DATA_BLOCK headers to identify block boundaries. ### Format 2 — SimaticML XML (exported LAD/FBD/SCL) The user provides `.xml` files exported from TIA Portal. These follow the SimaticML schema. Key navigation points: - `<SW.Blocks.FB>`, `<SW.Blocks.FC>`, `<SW.Blocks.OB>`, `<SW.Blocks.DB>` — block type - `<Interface>` → `<Section Name="Input|Output|InOut|Static|Temp|Constant">` — variable declarations - `<ObjectList>` → `<CompileUnit>` — individual networks - `<FlgNet>` inside CompileUnit — LAD/FBD network logic a