baremetal-startup

# Bare-metal startup ## Contract | Field | Bound contract | |---|---| | Trigger | Firmware never reaches `main()`, a new MCU is being brought up without a vendor HAL, or a custom `startup.s`, `Reset_Handler`, or crt0 is being written or debugged on Cortex-M or RISC-V. | | Authority | Read-only: emits startup code, linker symbol requirements, and diagnostics to chat; the user places them in the project. Rollback is not needed because no file is written. No remote mutation. | | Side effect | Chat output only. | | Done | The startup path from the reset vector to `main()` is stated step by step, the vector table layout and the `.data` and `.bss` loops are given for the target core, and every linker symbol the code uses is listed with the linker script line that defines it. | ## Inputs - Target core (Cortex-M0+, M3, M4F, M7, or RISC-V RV32 or RV64) and the vendor part. - The linker script, or at least its `MEMORY` regions and the symbols it exports. - Whether the firmware boots directly from flash or is launched by a bootloader at an offset. - Which C runtime is linked (newlib, newlib-nano, none) and whether C++ static constructors exist. ## Procedure 1. State the boot sequence for the core before writing code. On Cortex-M the hardware loads `SP` from vector 0 and branches to vector 1, `Reset_Handler`. On RISC-V the core starts at the reset address with `sp` undefined, so the first instruction sets it. Done when: the sequence is written as an ordered list from power-on to `m...