arm-cortex-m

Solid

Deep expertise in ARM Cortex-M architecture and peripherals

AI & Automation 814 stars 53 forks Updated today MIT

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Skill Content

# ARM Cortex-M Skill ## Overview This skill provides deep expertise in ARM Cortex-M architecture, including core configuration, peripheral programming, and low-level optimization for the most widely used embedded processor family. ## Capabilities ### CMSIS Integration - CMSIS-Core configuration and usage - CMSIS-Driver integration - CMSIS-DSP library utilization - CMSIS-RTOS abstraction - Device header file management ### NVIC Configuration - Interrupt priority configuration - Priority grouping setup - Vector table relocation - Interrupt enable/disable patterns - Nested interrupt handling ### Memory Protection Unit (MPU) - MPU region setup and configuration - Memory attribute configuration - Protection scheme design - Stack overflow protection - Peripheral isolation ### System Timers - SysTick timer configuration - DWT cycle counter usage - Timer-based profiling - Timestamp generation - Delay implementations ### Fault Handling - HardFault analysis and debugging - BusFault configuration - UsageFault detection - MemManage fault handling - Fault register interpretation ### Low-Level Optimization - ARM assembly for critical sections - Bit-banding operations - Atomic operations (LDREX/STREX) - Barrier instructions (DSB, DMB, ISB) - Compiler intrinsics ### Power Management - WFI/WFE instruction usage - Sleep mode entry/exit - Wake-up source configuration - Low-power mode selection - Power domain management ## Target Processes - `bsp-development.js` - BSP with Cortex-M s...

Details

Author
a5c-ai
Repository
a5c-ai/babysitter
Created
4 months ago
Last Updated
today
Language
JavaScript
License
MIT

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