verilog-sv-language

# Verilog/SystemVerilog Language Skill Expert skill for Verilog and SystemVerilog development following IEEE 1364 and IEEE 1800 standards. Provides deep expertise in synthesizable RTL code generation, proper construct usage, and modern coding practices. ## Overview The Verilog/SystemVerilog Language skill enables comprehensive HDL development for FPGA and ASIC designs, supporting: - IEEE 1800-2017 SystemVerilog standard - Verilog-2005 backward compatibility - Proper always_ff, always_comb, always_latch usage - SystemVerilog interfaces and modports - Parameterized modules with localparam - Packed and unpacked arrays - Packages and imports ## Capabilities ### 1. Proper Always Block Usage Use SystemVerilog always block variants correctly: ```systemverilog // Sequential logic - always_ff always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin counter <= '0; state <= IDLE; end else begin counter <= counter + 1'b1; state <= next_state; end end // Combinational logic - always_comb always_comb begin // Default assignments prevent latches next_state = state; output_valid = 1'b0; case (state) IDLE: begin if (start) next_state = RUN; end RUN: begin output_valid = 1'b1; if (done) next_state = IDLE; end default: next_state = IDLE; endcase end // Intentional latch - always_latch (rare) always_latch begin if (enable) latch_out = data_in; end ``` ### 2. Parameterized Modules Create reusable ...