vhdl-language

# VHDL Language Skill Expert skill for VHDL (VHSIC Hardware Description Language) development following IEEE 1076 standards. Provides deep expertise in synthesizable VHDL code generation, coding guidelines, and best practices for FPGA design. ## Overview The VHDL Language skill enables comprehensive VHDL development for FPGA and ASIC designs, supporting: - IEEE 1076-2019 standard compliance - Synthesizable code generation - Entity, architecture, package, and component declarations - Synchronous process design with proper reset handling - Vendor-specific synthesis attributes - Testbench generation with assert statements - Detection and fix of common coding anti-patterns ## Capabilities ### 1. Entity and Architecture Definition Generate proper entity and architecture structures: ```vhdl -- Example: Parameterized FIFO Entity library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sync_fifo is generic ( DATA_WIDTH : positive := 8; DEPTH : positive := 16; ALMOST_FULL_THRESHOLD : natural := 14; ALMOST_EMPTY_THRESHOLD : natural := 2 ); port ( clk : in std_logic; rst_n : in std_logic; -- Write interface wr_en : in std_logic; wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0); full : out std_logic; almost_full : out std_logic; -- Read interface rd_en : in std_logic; rd_data : out std_logic_vector(DATA_WIDTH-1 downto 0); emp...